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19-2122; Rev 2; 7/03
12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface
General Description
The MAX5742 quad, 12-bit, low-power, buffered voltage-output, digital-to-analog converter (DAC) is packaged in a space-saving 10-pin MAX package (5mm 3mm). The wide supply voltage range of +2.7V to +5.5V and 229A supply current accommodates lowpower and low-voltage applications. DAC outputs employ on-chip precision output amplifiers that swing Rail-to-Rail(R). The MAX5742's reference input accepts a voltage range from 0 to VDD. In power-down the reference input is high impedance, further reducing the system's total power consumption. The 20MHz, 3-wire SPITM, QSPITM, MICROWIRETM and DSP-compatible serial interface saves board space and reduces the complexity of opto- and transformerisolated applications. The MAX5742 on-chip power-on reset (POR) circuit resets the DAC outputs to zero and loads the output with a 100k resistor to ground. This provides additional safety for applications that drive valves or other transducers that need to be off on power-up. The MAX5742's software-controlled powerdown reduces supply current to less than 0.3A and provides software-selectable output loads (1k, 100k, or high impedance) while in power-down. The MAX5742 is specified over the -40C to +125C automotive temperature range. o Ultra-Low Power Consumption 229A at VDD = +3.6V 271A at VDD = +5.5V o Wide +2.7V to +5.5V Single-Supply Range o 10-Pin MAX Package o 0.3A Power-Down Current o Guaranteed 12-Bit Monotonicity (1LSB DNL) o Safe Power-Up Reset to Zero Volts at DAC Output o Three Software-Selectable Power-Down Impedances (100k, 1k, Hi-Z) o Fast 20MHz 3-Wire SPI, QSPI, and MICROWIRECompatible Serial Interface o Rail-to-Rail Output Buffer Amplifiers o Schmitt-Triggered Logic Inputs for Direct Interfacing to Optocouplers o Wide -40C to +125C Operating Temperature Range
Features
MAX5742
Applications
Automatic Tuning Gain and Offset Adjustment Power Amplifier Control Process Control I/O Boards Battery-Powered Instruments VCO Control
PART MAX5742EUB MAX5742AUB
Ordering Information
TEMP RANGE -40C to +85C -40C to +125C PIN-PACKAGE 10 MAX 10 MAX
Pin Configuration
TOP VIEW
CS 1 SCLK 2 3 4 5 10 OUTD 9 OUTC OUTB OUTA REF
Functional Diagram appears at end of data sheet. Rail-to-Rail is a registered trademark of Nippon Motorola, Inc. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor, Corp.
VDD GND DIN
MAX5742
8 7 6
MAX
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface MAX5742
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V OUT_, SCLK, DIN, CS, REF to GND...............-0.3 to (VDD+0.3V) Maximum Continuous Current Into Any Pin......................50mA Continuous Power Dissipation (TA = +70C) 10-Pin MAX (derate 6.9 mW/C above +70C) ..........555mW Operating Temperature Range .........................-40C to +125C Junction Temperature.......................................-65C to +150C Storage Temperature Range ............................-65C to +150C Lead Temperature (soldering, 10s) ................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5k, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are VDD = +5V, TA = +25C.)
PARAMETER STATIC ACCURACY (Note 1) Resolution Integral Nonlinearity Error Differential Nonlinearity Error Zero-Code Error Zero-Code Error Tempco Gain Error Gain-Error Tempco Power-Supply Rejection Ratio REFERENCE INPUT Reference Input Voltage Range Reference Input Impedance Power-Down Reference Current DAC OUTPUT Output Voltage Range DC Output Impedance Short-Circuit Current Wake-Up Time Output Leakage Current No load (Note 4) Code = 800 hex VDD = +3V VDD = +5V VDD = +3V VDD = +5V Power-down mode = output high impedance 0 0.8 15 48 8 8 18 VDD V mA s nA VREF RREF In operation In power-down mode In power-down mode (Note 3) 0 32 45 2 1 10 VDD 63 V k M A PSRR Code = FFF hex, VDD = 10% GE Code = FFF hex 0.26 58.8 N INL DNL OE (Note 2) Guaranteed monotonic (Note 2) Code = 000 0.4 2.3 3 12 2 16 1 1.5 Bits LSB LSB % of FS ppm/C % of FS ppm/C dB SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5k, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are VDD = +5V, TA = +25C.)
PARAMETER DIGITAL INPUTS (SCLK, DIN, CS) Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance DYNAMIC PERFORMANCE Voltage Output Slew Rate Voltage Output Settling Time Digital Feedthrough Digital-Analog Glitch Impulse DAC-to-DAC Crosstalk POWER REQUIREMENTS Supply-Voltage Range Supply Current with No Load Power-Down Supply Current VDD IDD IDDPD All digital inputs at 0 or VDD = 3.6V All digital inputs at 0 or VDD = 5.5V All digital inputs at 0 or VDD = 5.5V 2.7 229 271 0.29 5.5 395 420 1 V A A SR 400 hex to C00 hex (Note 5) Any digital inputs from 0 to VDD Major carry transition (code 7FF hex to code 800 hex) 0.5 4 0.1 12 2.4 10 V/s s nV-s nV-s nV-s VIH VIL IIN CIN VDD = +3V, +5V VDD = +3V, +5V Digital inputs = 0 or VDD 0.1 5 0.7 x VDD 0.3 x VDD 1 V V A pF SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5742
TIMING CHARACTERISTICS
(VDD = 2.7V to 5.5V, GND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SCLK Clock Frequency SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup Time SCLK Fall to CS Rise Setup Time DIN to SCLK Fall Setup Time DIN to SCLK Fall Hold Time CS Pulse Width High SYMBOL f SCLK tCH tCL tCSS tCSH tDS tDH tCSW CONDITIONS MIN 0 25 25 10 10 15 0 80 TYP MAX 20 UNITS MHz ns ns ns ns ns ns ns
Note 1: Note 2: Note 3: Note 4: Note 5:
DC specifications are tested without output loads. Linearity guaranteed from code 115 to code 3981. Limited with test conditions. Offset and gain error limit the FSR. Guaranteed by design.
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12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface MAX5742
__________________________________________Typical Operating Characteristics
(VREF = VDD, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. CODE, TA = +25C
MAX5742 toc01
DIFFERENTIAL NONLINEARITY vs. CODE, TA = +25C
MAX5742 toc02
TOTAL UNADJUSTED ERROR vs. CODE, TA = +25C
0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 VDD = +5V 0 512 1024 1536 2048 2560 3072 3584 4096 CODE VDD = +3V
MAX5742 toc03
16 12 8 INL (LSB)
1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4
1.0 TOTAL UNADJUSTED ERROR (%)
4 0 -4 -8 -12 -16 0
VDD = +5V
VDD = +3V
-0.6 -0.8 -1.0
512 1024 1536 2048 2560 3072 3584 4096 CODE
0
512 1024 1536 2048 2560 3072 3584 4096 CODE
INTEGRAL NONLINEARITY vs. CODE, TA = -40C
MAX5742 toc04
DIFFERENTIAL NONLINEARITY vs. CODE, TA = -40C
MAX5742 toc05
TOTAL UNADJUSTED ERROR vs. CODE, TA = -40C
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 VDD = +5V 0 512 1024 1536 2048 2560 3072 3584 4096 CODE VDD = +3V
MAX5742 toc06
16 12 8 INL (LSB) 4 0 -4 -8 -12 -16 0 VDD = +3V VDD = +5V
1.0 0.8 0.6 0.4 0.2 LSB 0 -0.2 -0.4 -0.6 -0.8
1.0 TOTAL UNADJUSTED ERROR (%)
512 1024 1536 2048 2560 3072 3584 4096 CODE
-1.0 0 512 1024 1536 2048 2560 3072 3584 4096 CODE
INTEGRAL NONLINEARITY vs. CODE, TA = +125C
MAX5742 toc07
DIFFERENTIAL NONLINEARITY vs. CODE, TA = +125C
MAX5742 toc08
TOTAL UNADJUSTED ERROR vs. CODE, TA = +125C
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 VDD = +5V 0 512 1024 1536 2048 2560 3072 3584 4096 CODE VDD = +3V
MAX5742 toc09
16 12 8 INL (LSB)
1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8
1.0 TOTAL UNADJUSTED ERROR (%)
4 0 -4 -8 -12 -16 0
VDD = +5V
VDD = +3V
512 1024 1536 2048 2560 3072 3584 4096 CODE
-1.0 0 512 1024 1536 2048 2560 3072 3584 4096 CODE
4
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12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface MAX5742
Typical Operating Characteristics (continued)
(VREF = VDD, TA = +25C, unless otherwise noted.)
WORST-CASE INL AND DNL vs. TEMPERATURE
MAX5742 toc10
SOURCE-AND-SINK CURRENT CAPABILITY (VDD = +3V)
MAX5742 toc11
SOURCE-AND-SINK CURRENT CAPABILITY (VDD = +5V)
4.5 4.0 3.5 VOUT (V) 3.0 2.5 2.0 1.5 1.0 CODE = C00 HEX, SOURCING CURRENT FROM OUT_ CODE = 400 HEX, SINKING CURRENT INTO OUT_ CODE = 000 HEX, SINKING CURRENT INTO OUT_ 0 2 4 6 8 10 12 14 16 CODE = FFF HEX, SOURCING CURRENT FROM OUT_
MAX5742 toc12 MAX5742 toc15
16 12 8 INL AND DNL (LSB) MAXIMUM INL
3.0 2.5 2.0 VOUT (V) 1.5 1.0 CODE = C00 HEX, SOURCING CURRENT FROM OUT_ CODE = 400 HEX, SINKING CURRENT INTO OUT_ CODE = 000 HEX, SINKING CURRENT INTO OUT_ 0 2 4 6 8 10 12 14 CODE = FFF HEX, SOURCING CURRENT FROM OUT_
5.0
4 0 -4 -8 -12 -16 -40 -20
MAXIMUM DNL
MINIMUM DNL MINIMUM INL
0.5 0 0 80 TEMPERATURE (C) 20 40 60 100 120
0.5 16 0
ISOURCE/SINK (mA)
ISOURCE/SINK (mA)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5742 toc13
POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
POWER-DOWN SUPPLY CURRENT (nA)
MAX5742 toc14
SUPPLY CURRENT vs. CS INPUT VOLTAGE
900 800 SUPPLY CURRENT (A) 700 600 500 400 300 200 100 VDD = +3V VDD = +5V
480 CODE = 0 x 800 400 SUPPLY CURRENT (A) 320 CODE = 0 x 000 240 160 80 0 2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V) CODE = 0 x FFF
300 250 200 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0 5.5 0 1 2 3 4 5 SUPPLY VOLTAGE (V) CS INPUT VOLTAGE (V)
SUPPLY CURRENT vs. TEMPERATURE
280 SUPPLY CURRENT (A) 270 260 250 240 230 220 210 200 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) VDD = 3.6V VDD = 5.5V
MAX5742 toc16
290
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12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface MAX5742
Typical Operating Characteristics (continued)
(VREF = VDD, TA = +25C, unless otherwise noted.)
FULL-SCALE SETTLING TIME (VDD = +5V) FULL-SCALE SETTLING TIME (VDD = +5V)
VSCLK, 5V/div
MAX5742 toc17
MAX5742 toc18
VSCLK, 5V/div
VOUT_ 1V/div CODE 000 TO FFF HEX RL = 5k CL = 200pF 1s/div CODE FFF TO 000 HEX RL = 5k CL = 200pF 1s/div
VOUT_ 1V/div
HALF-SCALE SETTLING TIME (VDD = +3V)
HALF-SCALE SETTLING TIME (VDD = +3V)
MAX5742 toc20
MAX5742 toc19
VSCLK, 5V/div
VSCLK, 5V/div
VOUT_ 1V/div CODE 400 TO C00 HEX RL = 5k CL = 200pF 1s/div CODE C00 TO 400 HEX RL = 5k CL = 200pF 1s/div
VOUT_ 1V/div
EXITING POWER-DOWN (VDD = +5V)
MAX5742 toc21
DIGITAL-TO-ANALOG GLITCH IMPULSE (VDD = +5V)
VSCLK, 5V/div
MAX5742 toc22
SCLK, fSCLK = 500kHz 2V/div
CODE 800 HEX
VOUT_ 1V/div CODE 7FF HEX to 800 HEX
VOUT_ AC-COUPLED, 20mV/div
5s/div
1s/div
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12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface MAX5742
____________________________Typical Operating Characteristics (continued)
(VREF = VDD, TA = +25C, unless otherwise noted.)
DIGITAL-TO-ANALOG GLITCH IMPULSE (VDD = +3V) DIGITAL-TO-ANALOG GLITCH IMPULSE (VDD = +5V)
SCLK, fSCLK = 500kHz, 2V/div
MAX5742 toc23
MAX5742 toc24
SCLK, fSCLK = 500kHz 2V/div
CODE 7FF HEX to 800 HEX
VOUT_ AC-COUPLED, 20mV/div CODE 800 HEX to 7FF HEX 1s/div
VOUT_ AC-COUPLED, 20mV/div
1s/div
DIGITAL-TO-ANALOG GLITCH IMPULSE (VDD = +3V)
MAX5742 toc25
POWER-ON RESET, FAST RISE TIME (VDD = +5V)
SCLK, fSCLK = 500kHz, 2V/div
MAX5742 toc26
VDD 2V/div
VOUT_ AC-COUPLED, 20mV/div CODE 800F HEX to 7FF HEX 1s/div 20s/div
VDD RISE TIME = 20s
VOUT_ AC-COUPLED, 10mV/div
POWER-ON RESET, SLOW RISE TIME (VDD = +5V)
POWER-ON RESET, FAST RISE TIME (VDD = +3V)
VDD 2V/div
MAX5742 toc27
MAX5742 toc28
VDD 2V/div VDD RISE TIME = 20s
VDD RISE TIME = 76s
VOUT_ AC-COUPLED, 2mV/div
VOUT_ AC-COUPLED, 10mV/div
40s/div
20s/div
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12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface MAX5742
Typical Operating Characteristics (continued)
(VREF = VDD, TA = +25C, unless otherwise noted.)
POWER-ON RESET, SLOW RISE-TIME (VDD = +3V)
MAX5742 toc29
CLOCK FEEDTHROUGH (VDD = +5V)
MAX5742 toc30
VDD 2V/div VDD RISE TIME = 72s
SCLK, 2V/div
VOUT_ AC-COUPLED, 2mV/div
CODE = 800 HEX, 2s/div fSCLK = 50kHz 2s/div
VOUT_ AC-COUPLED, 1mV/div
40s/div
CLOCK FEEDTHROUGH (VDD = +3V)
MAX5742 toc31
LINE TRANSIENT RESPONSE (VDD = +5V)
SCLK, 2V/div
MAX5742 toc32
VDD, AC-COUPLED, 100mV/div
CODE = 800 HEX, 2s/div fSCLK = 50kHz 2s/div
VOUT_ AC-COUPLED, 1mV/div
VOUT_ AC-COUPLED, 10mV/div
20s/div
LINE TRANSIENT RESPONSE (VDD = +3V)
MAX5742 toc33
CROSSTALK (VDD = +5V)
MAX5742 toc34
VDD, AC-COUPLED, 100mV/div
CODE FFF HEX to 00B HEX
VOUTA, 2V/div
VOUT_ AC-COUPLED, 10mV/div
VOUTB, AC-COUPLED, 2mV/div
20s/div
4s/div
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12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface
Pin Description
PIN 1 2 3 4 5 6 7-10 NAME CS SCLK VDD GND DIN REF OUTA -OUTD Chip-Select Input Serial-Clock Input Power-Supply Input Ground Serial Data Input External Reference Voltage Input DAC Voltage Outputs. Power-on reset sets DAC registers to zero, and internally connects OUT to GND with 100k resistor. FUNCTION
MAX5742
Detailed Description
The MAX5742 contains four 12-bit, voltage-output, lowpower digital-to-analog converters (DACs). Each DAC employs a resistor string architecture that converts a 12-bit digital input word to an equivalent analog output voltage proportional to the applied reference voltage. The MAX5742 shares one reference input (REF) between all four DACs. The MAX5742 includes rail-torail output buffer amplifiers for each DAC, and input logic for simple microprocessor (P), and CMOS interfaces. The power-supply range is from +2.7V to +5.5V (Functional Diagram). The MAX5742's reference input accepts a voltage range from 0 to VDD. In power-down mode the reference input is high impedance. The MAX5742 is compatible with the 3-wire SPI, QSPI, MICROWIRE and DSP serial interface with Schmitt-triggered logic inputs.
and (GND to VREF) output voltage range. The buffers are unity-gain stable with CL = 200pF and RL = 5k. Buffer amplifiers are disabled during power-up and individual DAC outputs are shorted to GND through a 100k resistor. Buffer amplifiers can individually or altogether be powered-down by programming the input register control bits. During power down, contents of the input and DAC registers remain the same. On wake-up, all DAC outputs are restored to their prepower-down voltage values.
Power-Down Mode
In power-down mode, the DAC outputs are programmed to one of three output states, 1k, 100k, or floating (Table 1). The REF input is high impedance (2M typ) to conserve current drain from the system reference; therefore, the system reference does not have to be powered-down. The DAC outputs return to the values contained in the registers when brought out of power-down. The recovery time, from total powerdown to power-up, is 8s. This extra time is needed to allow the internal bias to wake-up. Power-down mode reduces current consumption to 0.3A.
Reference Input and DAC Output Range
The reference input accepts positive DC and AC signals. The voltage at REF sets the full-scale output voltage of the four DACs. The reference input voltage range is 0 to VDD. The impedance at REF is 45k. The voltage at REF can vary from GND to VDD. The output voltages (VOUT_) are represented by a digitally programmable voltage source as: VOUT_ = (VREF D) / 212 where D is the decimal equivalent of binary DAC input code ranging from 0 to 4095. VREF is the voltage at REF.
3-Wire Serial Interface
The MAX5742 digital interface is a standard 3-wire connection compatible with SPI/QSPI/MICROWIRE/DSP interfaces. The chip-select input (CS) frames the serial data loading at DIN. Immediately following CS high-tolow transition, the data is shifted synchronously and latched into the input register on the falling edge of the serial clock input (SCLK). After 16 bits have been loaded into the serial input register, it transfers its contents to the DAC latch. CS may then either be held low or brought high. CS must be brought high for a minimum of 80ns before the next write sequence, since a
9
Output Buffer Amplifiers
All DACs are internally buffered at the output. The buffer amplifiers have both rail-to-rail common mode
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12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface MAX5742
Table 1. Power-Down Mode Control
EXTENDED CONTROL C3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D11-D5 X X X X X X X X X X X X X X X X X X X X D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 DATA BITS D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DAC A DAC A DAC A DAC A DAC B DAC B DAC B DAC B DAC C DAC C DAC C DAC C DAC D DAC D DAC D DAC D DAC A-D DAC A-D DAC A-D DAC A-D DAC O/P, wakeup Floating output Output is terminated with 1k Output is terminated with 100k DAC O/P, wakeup Floating output Output is terminated with 1k Output is terminated with 100k DAC O/P, wakeup Floating output Output is terminated with 1k Output is terminated with 100k DAC O/P, wakeup Floating output Output is terminated with 1k Output is terminated with 100k DAC O/P, wakeup Floating output Output is terminated with 1k Output is terminated with 100k DESCRIPTION FUNCTION
X = Don't care
write sequence is initiated on a falling edge of CS. Not keeping CS low during the first 15 SCLK cycles discards input data. The serial clock (SCLK) can idle either high or low between transitions. The MAX5742 has two internal registers per DAC, the input register and the DAC register. The input register holds the data that is waiting to be shifted to the DAC register. All input registers can be loaded without updating the output. This function is useful when all outputs need to be updated at the same time. The input register can be made transparent. When the input register is transparent, the data written into DIN loads directly to the DAC register and the output is updated. The DAC output is not updated until data is written to the DAC register. See Table 2 for a list of serial-interface programming commands.
Power-On Reset (POR)
The MAX5742 has an internal POR circuit. At power-up all DACs are powered-down and OUT_ is terminated to GND through 100k resistors. Contents of input and DAC registers are cleared to all zero. An 8s recovery time after issuing a wake-up command is needed before writing to the DAC registers. Power-down mode control commands can be applied immediately with no recovery time. C3-C0 are control bits. The data bits D11 to D0 are in straight binary format. All zeros correspond to zero scale and all ones correspond to full scale.
Digital Inputs
The digital inputs are compatible with CMOS logic. In order to save power and reduce input to output coupling, SCLK and DIN input buffers are powered down immediately after completion of shifting 16 bits into the input shift register. A high to low transition at CS powers up SCLK and DIN input buffers.
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12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface MAX5742
CONTENTS OF SHIFT REGISTER D15 (MSB) C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D0 (LSB) D1 D0
Figure 1. 16-Bit Input Word
tCL
tCH
SCLK
X
1
2
3
4
5
6
16
X
tOS
tOH
DIN
X
C3
C2
C1
C0
D11
D10
D1
D0
X
tCSPWH
tCSS
tCSH
CS
Figure 2. Timing Diagram
Applications Information
Unipolar Output
The typical application circuit (Figure 3) shows the MAX5742 configured for a unipolar output, where the output voltages and the reference inputs have the same polarity. Table 3 lists the unipolar output codes.
where NB is the decimal value of the DACs binary input code. Table 4 shows digital codes (offset binary) and corresponding output voltages for the circuit in Figure 4.
Power Supply and Layout Considerations
Careful PC board layout is important for optimal system performance. To reduce noise injection and digital feedthrough, keep analog and digital signals separate. Ensure that that the return path from GND to the supply ground is short and low impedance. Use a ground plane. Bypass VDD to GND with a 0.1F capacitor as close as possible to VDD.
Bipolar Output
The MAX5742 can be configured for bipolar operation using a dual supply op amp (Figure 4). The transfer function for bipolar operation is: 2NB VOUT = VREF - 1 4096
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12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface MAX5742
Table 2. Serial-Interface Programming Commands
CONTROL C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 C2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 C1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 C0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 DATA BITS D11-D0 X X X X X X X X X X X X X X X DAC A B C D A B C D A B C D A-D A-D A-D FUNCTION Input register transparent, data shifted directly to DAC register, OUTA updated Input register transparent, data shifted directly to DAC register, OUTB updated Input register transparent, data shifted directly to DAC register, OUTC updated Input register transparent, data shifted directly to DAC register, OUTD updated Data shifted to input register, OUTA unchanged Data shifted to input register, OUTB unchanged Data shifted to input register, OUTC unchanged Data shifted to input register, OUTD unchanged Shift data from input register to DAC register, OUTA updated Shift data from input register to DAC register, OUTB updated Shift data from input register to DAC register, OUTC updated Shift data from input register to DAC register, OUTD updated Input registers transparent, data shifted directly to DAC registers, OUTA-OUTD updated Data shifted to input registers, OUTA-OUTD unchanged Shift data from input registers to DAC registers, OUTA-OUTD updated
X = Don't care
+2.7V TO +5.5V
R1
R2 V+
+2.7V TO +5.5V
REF IN OUT DAC_
VDD OUT_ DAC_
REF
VDD
VOUT
MAX6050
GND GND
OUT_ V-
MAX5742
MAX5742
R1 = R2
Figure 3. Typical Operating Circuit, Unipolar Output
Figure 4. Bipolar Output Circuit
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12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface MAX5742
Table 3. Unipolar Code Table
DAC CONTENTS 1111 1111 1111 ANALOG OUTPUT
Table 4. Bipolar Code Table
DAC CONTENTS 1111 1111 1111 ANALOG OUTPUT
4095 VREF 4096 2049 VREF 4096 VREF 2 2047 VREF 4096 1 VREF 4096
0
2047 + VREF 2048 1 + VREF 2048
0
-VREF
1000 0000 0001
1000 0000 0001 1000 0000 0000 0111 1111 1111
1000 0000 0000
1 2048 2047 2048
0111 1111 1111
0000 0000 0001 0000 0000 0000
-VREF
0000 0000 0001 0000 0000 0000
-VREF
Chip Information
TRANSISTOR COUNT: 14,458 PROCESS: BiCMOS
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12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface MAX5742
Functional Diagram
VDD REF
INPUT REGISTER A
DAC REGISTER A
12-BIT DAC A
OUTPUT BUFFER
OUTA
RESISTOR NETWORK
INPUT REGISTER B
DAC REGISTER B
12-BIT DAC B
OUTPUT BUFFER
OUTB
RESISTOR NETWORK
INPUT REGISTER C
DAC REGISTER C
12-BIT DAC C
OUTPUT BUFFER
OUTC
RESISTOR NETWORK
INPUT REGISTER D
DAC REGISTER D
12-BIT DAC D
OUTPUT BUFFER
OUTD
INPUT CONTROL LOGIC AND SHIFT REGISTER
RESISTOR NETWORK POWER-DOWN CONTROL LOGIC
MAX5742
CS
SCLK
DIN
GND
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12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
10LUMAX.EPS
MAX5742
e
10
4X S
10
INCHES MAX DIM MIN A 0.043 A1 0.002 0.006 A2 0.030 0.037 D1 0.116 0.120 D2 0.114 0.118 E1 0.116 0.120 0.118 E2 0.114 0.199 H 0.187 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S 0 6
MILLIMETERS MAX MIN 1.10 0.15 0.05 0.75 0.95 3.05 2.95 3.00 2.89 3.05 2.95 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0 6
H y 0.500.1 0.60.1
1
1
0.60.1
TOP VIEW
BOTTOM VIEW
D2 GAGE PLANE A2 A b A1 D1
E2
c
E1 L1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0061
1 1
I
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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